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Multistandard Sound IF
TDA 6160-2S
Preliminary Data
Bipolar IC
Features
q q q q q q q q
Sound carrier mixer VCO Programmable Divider Reference divider with crystal oscillator Phase comparator Operational amplifier for PLL filter I2C bus interface 3 identical FM channels with limiter amplifiers and coincidence demodulators.
P-SDIP-30
Type TDA 6160-2S
Ordering Code Q67000-A5184
Package P-SDIP-30
Functional Description Multistandard sound IF-device consisting of a mixer as a frequency converter, a voltage-controlled oscillator (VCO) that can be continously tuned in 10-kHz increments with crystal accuracy by means of a PLL, and three following parallel FM-limiter amplifiers with coincidence demodulators. The switching functions and setting of the PLL are controlled on an I2C bus. Application For use in satellite receivers.
Semiconductor Group
126
08.93
TDA 6160-2S
Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function Quartz oscillator PD-output / integrator input (fREF, fCy) Integrator output (VD) VCO Chip address switching (CA) Demodulator circuit (IF-1) Demodulator circuit (IF-1) AF-output 1 Demodulator circuit (IF-2) Demodulator circuit (IF-2) AF-output 2 Demodulator circuit (IF-3) Demodulator circuit (IF-3) AF-output 3 NC NC IF-input 3
VS (analog)
IF-input 2 Ground (analog) IF-input 1 IF-reference Mixer output 2 Mixer output 1 Mixer input (reference) Mixer input Ground (digital)
VS (digital)
I2C bus (SCL) I2C bus (SDA)
Semiconductor Group
127
TDA 6160-2S
Pin Functions
Pin 1
Pin 2/3
Semiconductor Group
128
TDA 6160-2S
Pin 4
Pin 6/7/8; 9/10/11; 12/13/14
Semiconductor Group
129
TDA 6160-2S
Pin 21; 19; 17/22
Pin 23/24/25/26
Semiconductor Group
130
TDA 6160-2S
Pin 5; 29
Pin 30
Semiconductor Group
131
TDA 6160-2S
Block Diagram Semiconductor Group 132
TDA 6160-2S
Circuit Description The sound intermediate frequencies contained in the baseband of a demodulated FM satellite signal can lie between 5 and 9 MHz. This band of frequencies is applied ready filtered to the input of the converter mixer. The purpose of this mixer is to convert the different sound IFs in the baseband to fixed output frequencies (eg 10.7/10.52 MHz). These frequencies are then fed by external filters to the inputs of the three sound IF-amplifiers. The VCO of the mixer can be continuously tuned between 14.5 and 20 MHz in 10-kHz increments with crystal accuracy by means of a PLL-circuit. The setting of the programmable divider and the cutting in and out of the sound IF-amplifiers are controlled on the I2C bus. Pin 5 (CA) offers two switchable chip addresses to enable parallel operation of two devices. All pins are guarded against electrostatic discharge. SCL and SDA include special protective structures to permit continued bus operation when the device is switched off. PLL The VCO-signal, DC coupled internally, is applied to the PLL-input. It passes through a programmable divider (N = 1024 to 2047) and is then compared to a reference frequency (fREF = 10 kHz) in a digital frequency/phase detector. This frequency is derived from a 4-MHz crystal oscillator whose signal is divided by 400. The phase detector has a charge-pump push-pull current output. If the negative edge of the divided VCO-signal appears before the negative edge of the reference signal, the current source I+ will pulse for the duration of the phase difference. In the reverse case it is the current sink I-. If both signals are in-phase, the output is high-impedance and the PLL is locked in. The current pulses are filtered by means of an integrator (internal operational amplifier with external RC-circuitry). The pump current can be switched between the two values 1 and 5 by software with a control bit 5I. This permits a change in the control response during and after the lock-in state. I2C Bus Interface Information is exchanged between the processor and the sound IF-device on an asynchronous bidirectional data bus. The timing for this comes from the processor (input SCL), while pin SDAfunctions as an input or output depending on the direction of the data (open collector; external pull-up resistor). The data from the processor go to an I2C bus controller and are filled in registers (latches 0 to 2) according to their function. When the bus is not busy, both lines are in marking state (SDA, SCL are high). Each telegram begins with the start condition: SDA goes low while SCL remains high. All further exchanges of information are while SCL is low and are read by the controller with the positive clock edge. If SDA goes high while the clock is high, the PLL recognizes this as a stop condition and thus the end of the telegram. For what follows, refer to the table of logic assignments below. All telegrams are transferred byte by byte, followed by a ninth clock pulse during which the controller pulls the SDA-line to low (i.e. acknowledge condition). The first byte consists of seven address bits with which the processor selects the PLL from among several peripheral devices (chip select). The
Semiconductor Group
133
TDA 6160-2S
eighth bit is always low. The first bit of the first or third data byte in the data part of the telegram determines whether a divider ratio or control information will follow. In every case the first byte must be followed by a byte of the same data type (or a stop condition). When the supply voltage is applied, a power-on reset circuit prevents the PLL from pulling the SDA-line to low and thus blocking the bus. Logic Allocations Address byte Progr. divider byte 1 Progr. divider byte 2 Control information Address byte 1 Address byte 2 0 0 n4 1 0 0 1 0 n3 5I 1 1 0 n10 n2 Z2 0 0 0 n9 n1 Z1 0 0 0 n8 n0 Z0 0 0 MA1 n7 0 T2 1 1 MA0 n6 0 T1 0 1 R/W n5 0 T0 0 0 A A A A A A = H44 = H46
Chip address (CA) pin 5 on:
ground = address byte 1 VS or open = address byte 2
Test Mode T2, T1, T0 = 0, 0, 0 T2, T1, T0 = 1, 0, 0 T2, T1, T0 = 1, 1, 0 T2, T1, T0 = 1, 1, 1 T2, T1, T0 = 0, 1, 1 normal operation pin 2 = fREF pin 2 = fCy pin 2 = tristate pin 2 = high-impedance = pin 3 high-impedance
IF-Muting Circuits Z2, Z1, Z0 = 0, 0, 0 Z2, Z1, Z0 = 0, 0, 1 Z2, Z1, Z0 = 0, 1, 0 Z2, Z1, Z0 = 0, 1, 1 Z2, Z1, Z0 = 1, 0, 0 Z2, Z1, Z0 = 1, 0, 1 Z2, Z1, Z0 = 1, 1, 0 Z2, Z1, Z0 = 1, 1, 1 normal operation IF 3 IF 2 IF 1 = on; IF 2/IF 3 = off IF 1 IF 1 = off; IF 2 = on; IF 3 = off IF 3 = on; IF 1/IF 2 = off IF 1, IF 2, IF 3 = off = off (output 14 high-impedance) = off (output 11 high-impedance) = off (output 8 high-impedance)
Semiconductor Group
134
TDA 6160-2S
Telegram Examples Start-AB-DB1-DB2-CI-Stop Start-AB-CI-DB1-DB2-Stop Start-AB-DB1-Stop Start-AB-CI-Stop Start AB DB1 DB2 CI Stop = start condition = address byte = divider byte 1 = divider byte 2 = control information = stop condition
Converter Mixer + VCO In the converter mixer the sound subcarriers (frequency band approx. 5 to 9 MHz) contained in the baseband of the received composite signal are converted to an output frequency of 10.52 MHz or 10.7 MHz for example. The two mixer outputs are designed as open-collector outputs. The VCO has internal feedback and its frequency of 15.5 to 19.7 MHz is determined by an external resonant circuit with a varactor diode that is tuned by the PLL. The resonant circuit is connected to the supply voltage by its low side.
IF-Limiter with Demodulators The limiter amplifiers are implemented as balanced five-stage, capacitively coupled differential amplifiers. All there limiter inputs have a common reference (pin 22). The output signals of the limiter amplifiers are fed direct and via an external phase-shifter circuit to the coincidence demodulators. The AF-signals can be brought out an disconnectible (by Z2, Z1, Z0) AF output stages. The outputs are high-impedance when they are disconnected.
Semiconductor Group
135
TDA 6160-2S
Absolute Maximum Ratings TA = 0 to 70 C Parameter Supply voltage AF-output AF-output Demodulators IF-inputs Mixer outputs VCO Crystal oscillator Junction temperature Storage temperature Thermal resistance Symbol min. Limit Values max. 6 3 V mA V V V V V V C C K/W 0 - 1.5 0 0 Unit
V18, V28 I8, I11, I14 V8, V11, V14 V6/7, V9/10, V12/13 V17, V19, V21 V23, V24 V4 V1 Tj Tstg Rth SA
V16 V16 V16
7 7 0 0 1.5 150 125 65
All voltage values are referred to ground (pin 20, pin 27), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from VS across the designated pin), it has a positive sign. Operating Range Supply voltage Input frequency range of converter mixer Input frequency range of sound IF-amplifiers (- 3 dB) VCO-frequency Ambient temperature
V18, V28 fI26 fI17, 19, 21 fO4 TA
4.5 5 5 5 0
5.5 9 15 20 70
V MHz MHz MHz C
Semiconductor Group
136
TDA 6160-2S
Characteristics VS = 5 V; TA = 25 C Parameter Current drain (analog section) Current drain (digital section) Phase-detector charge current Symbol min. Limit Values typ. 33 20 32 160 35 40 250 max. 42 44 75 360 mA mA A A I 5I Unit Test Condition
I18 I28 IPD
Mixer Static Characteristics Mixer output currents Output-current difference Mixer inputs Dynamic Characteristics Input voltage for IMA > 60 dB
I23, 24 I23 - I24 V25, 26
1.1 100 3
3.5
mA A V
V25 = V26 V25 = V26
V26
180
230
mVrms SC1 = 6 MHz; SC2 = 6.5 MHz; SC3 = 7 MHz; VSC1 = VSC2 = VSC3 MHz k MHz
Input-frequency band Input-resistance Output-frequency band Frequency band of VCO Mixer gain Output-voltage range on mixer
fI26 R25/26 f023/24
f4
5 4 11 15 -8 -4
9
20 -2
MHz dB V
GMi
RL = 470
IMA > 55 dB; V25/26 < 180 mVrms
V18
- 0.4
V18
max
Semiconductor Group
137
TDA 6160-2S
Characteristics (cont'd) Parameter Symbol min. Sound IF (for all three amplifiers) Static and Dynamic Characteristics Input-frequency band Input voltage to activate limiting (VqAF - 3 dB) AF-output voltage Limit Values typ. max. Unit Test Condition
f17, 19, 21
5
15
MHz
fI17, 19, 21 V17, 19, 21 V8, 11, 14
150 70 220 250 300 V mV = 10.7 MHz; f = 30 kHz; fmod = 1 kHz
fI17, 19, 21
= 10.7 MHz; f = 30 kHz; VI17, 19, 21 = 10 mV, fmod = 1 kHz
Distortion factor
THD8, 11, 14
0.2
%
fI17, 19, 21
= 10.7 MHz; f = 30 kHz; VI17, 19, 21 = 10 mV, fmod = 1 kHz
AM-rejection AM-rejection AF-output DC-voltage Design Notes Sound IF-input resistance
aAM aAM
45 25 2.2
dB dB V
VI17, 19, 21 = 20 to 100 mV; m = 30% VI17 = 2 mV; m = 30%
R17/22 R19/22 R21/22 R6/7 R9/10 R12/13 R8, 11, 14 VIF8, 11, 14 aH
800
Demodulator input resistance
30
k
AF-output resistance Residual IF-voltage Hum suppression (without deemphasis)
100 5 25
mV dB
VS = 5 V; VH = 250 mVpp; fH = 50 Hz
Semiconductor Group
138
TDA 6160-2S
Characteristics (cont'd) Parameter Symbol min. I2C Bus (SCL, SDA) Edges SCL, SDA Rise time Fall time Shift clock SCL Frequency H-pulse width L-pulse width Start Setup time Hold time Stop Setup time Bus free Data change Setup time Hold time Inputs SCL, SDA Input voltage Limit Values typ. max. Unit Test Condition
tR tF fSCL tH tL tSUSTA tHDSTA tSUSTO tBUF tSUDAT tHDDAT VIH VIL IIH IIL VQH VQL V5L V5H
4.5 0 2.4 0 4 4 4 4 4 4 1 1 2.4
1 300 100
s ns kHz s s s s s s s s
5.5 1 10 10 5.5 0.4 1 5.5
V V A A V V V V
Input current Output SDA (open collector) Output voltage Address byte 1 = L Address byte 2 = H or open
RL = 2.5 k IQL = 3 mA
Semiconductor Group
139
TDA 6160-2S
Test Circuit Semiconductor Group 140
TDA 6160-2S
Application Circuit Semiconductor Group 141
TDA 6160-2S
I2C Bus Timing Diagram
tSUSTA tHDSTA tH tL tSUDAT tHDDAT tSUSTO tBUF tF tR
Setup time (start) Hold time (start) H-pulse width (clock) L-pulse width (clock) Setup time (data change) Hold time (data change) Setup time (stop) Bus free time Fall time Rise time
All times referred to VIH and VIL values
Semiconductor Group
142
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